Arithmetic circuit for simultaneous generation of sum and carry signals



ARITHMETIC CIRCUIT FOR SIMULTANEOUS GENERATION Feb. 13, 1968 H. J. HEIJN 3,369,110

OF SUM AND CARRY SIGNALS Filed April 7, 1964 2 SheetS -Sheet l DECIMAL BINARY x =2957 =01o11-100o11o1 uuuszns y =3423 =o11o 101o 11111 CARRY c 1010 1111000111110 SUM x+y :6380 =11000-11'101100 FIG.1

1; 3 MEMdRY MATRIX- u x 3-1. i-1 am i ,i+1

F 6 INVENTOR.

HERMAN J. HEIJN ic-w' l AGEN United States Patent 3,369,110 ARITHM'ETIC CIRCUIT FOR SIMULTANE- In US. Patent 3,210,735 is disclosed how the logical connections not, or and and and hence all the con nections of the bivalent logic can be obtained with the aid of annular storage cores of a material having a rectangular magnetic hysteresis loop. In the said patent it is also stated that, at least in theory, it is not necessary to decompose logical connections of three or more variables into combinations of the above-mentioned logical operations, although for practical reasons this will usually be desirable or necessary for operations involving four or more variables. The said patent includes a table indicating how the ideas referred to can be realized for functions of one, two or three variables.

In the said patent there are described 'two examples of a computer which utilize the ideas above referred to. The computers concerned comprise substantially a matrix of storage cores provided with comparatively simple peripheral equipment and include one or more pulse generators for each row and a storage element in the form of a flip-flop or the like for each column.

Such computers have the disadvantage of slow speed when considered from an electronic standpoint. This is not attributable to the comparatively low speed of the storage cores but to the logic used. In fact, it is in the nature of the system described in the said patent that each addition is carried out as a series-process, that is to say digit position after digit position, while the calculation takes six or more basic time intervals or clock-pulse phases for each digit position.

It is the object of the present invention to obviate this disadvantage. This is achieved in that in every digit position the operations which have to be carried out with the digits of the numbers to be added together are carried out. Simultaneously by means of the peripheral equipment in the storage matrix, operations which are not dependent on the results of the operations at other digit positions, are carried out in a logical circuit common to the columns of the matrix. In the case of an addition of two numbers such is the case, for example, with the carry.

It has already been stated hereinbefore that the peripheral equipment for carrying out logical operations in the columns of the matrix independently of the results of the operations in other columns is comparatively very simple. The technical importance of the idea above set out resides in the fact that only a small extension renders the said equipment suitable for carrying out operations which have to be effected as a series-process. The use of this idea makes it possible to construct a computer, while not of ultra-high speed, at least comparatively simple and hence inexpensive. Such a machine can carry out an addition or subtraction of two numbers having about 10 decimal digit positions (corresponding to about 37 binary digit positions) within one ten thousandth of a second and a multiplication or division of two such numbers within one thousandth of a second. Such speeds are more than sufiicient for numerous uses, for example, computers of the so-called table type.

In order that the invention may be readily carried into affect, one embodiment thereof will now be described in detail, by way of example, with reference to the accom- 3,369,110 Patented Feb. 13, 1968 ICC panying diagrammatic drawings. The embodiment relates to a machine calculating in the binary system but this restriction is not essential. The important point is that all the operations which are not dependent on the results of operations at other digit positions are carired out simultaneously, and in phase, in the storage matrix for all the digit positions and that those operations which must necessarily be carried out sequentially take place in a separate logical circuit obtained by extension of the peripheral equipment which is present already for other reasons. This requires the operations to be decomposed into one set of operations to be carried out simultaneously and another set of operations to be carried out sequentially, a problem which lies wholly in the mathematiclogical field and will rarely meet with difliculties, although it is not always easy to find the optimum division.

FIGURE 1 shows, in tabular form, the manner in which, according to the invention, the sum of two numbers written in binary form is found;

FIGURE 2 shows, likewise in tabular form, a survey of the Boolean-algebraic formulae used;

FIGURE 3 shows a block diagram of one portion of the peripheral equipment of a storage matrix which relates to a single digit position in accordance with the invention;

FIGURES 4, 5 and 6 show tables which serve to explain the operation of this embodiment.

In FIGURE 1 it is illustrated in which manner the numbers x=2957 and y=3423 are added in a computer according to the invention. It appears that the carries or transfers which have to be handled at the four decimal digit positions of these numbers are 0, 1, 0 and 1 respectively (when counting the digit positions from the right to the left). These transfers are shown in FIGURE 1 in line c at the digit positions where they have to be handled, at the digit position to the left of the digit position where the relevant transfer is produced. The digits s s s and s, of the sum s=x+y of the two numbers x and y are found by calculating, at each digit position, the sum modulo 10 of the relevant digits x and y, of the numbers x and y and the transfer 0 to be handled at this digit position.

FIGURE 1 also shows the bivalent equivalent of this calculation of the sum of the numbers x and y.

FIGURE 2 shows the Boolean-algebraic formulae underlying the embodiment of the invention explained in detail hereinafter, as well as the importance of the auxiliary variables 17,, q, and r used therein. The latter magnitudes are to be regarded as abbreviations for the Boolean-algebraic functions shown in FIGURE 2. The correctness of these formulae can immediately be verified by writing the eight possible cases which may occur in the addition modulo 2 of three binary digits (0 or 1). See therefor, for example, R. Serell, Elements of Boolean Algebra for the Study of Information-Handling Systems (P.I.R.E., vol. 41, 1953, pages 1366 to 1380).

FIGURE 3 shows a block diagram of the portion of the peripheral equipment relating to a single digit position (or column), for the columns of the storage matrix (not shown) of a computer in which the invention is used. This portion is connected through two wires 1 and 2 to the storage elements of a column of the storage matrix. Let it be assumed that the storage elements are-storage cores, but this assumption is not essential. The illustrated portion of the peripheral equipment is connected through two wires 3, and 4 to the corresponding portion of the peripheral equipment for the preceding digit position and through two wires 3 and 4 to the corresponding portion of the peripheral equipment for the succeeding digit position. The wire 1 serves to lead a signal from the matrix to the relevant portion of the peripheral equipment and the wire 2, to lead a signal in the opposite sense. The signals in the wires 1 and 2, consist in the presence or absence of a pulse. The Wires 3'1 1 1 and 414,1 serve to transport a signal c produced in the preceding part of the peripheral equipment (which signal need not necessarily have the signification of a carry) to the illustrated portion of the peripheral equipment and the wires 3 and 4 serve to transport a signal 0111 produced in this portion of the peripheral equipment to the succeeding part thereof. The signals in the wires 3 and 4, are direct voltages or direct currents such that the voltages or currents for the same value of the subscript i are always different in two wires 3 and 4 these voltages or currents interchanging when the value of the relevant signal changes from to 1 or conversely.

The circuit shown shown in FIGURE 3 comprises two flip-flops U and V two and-gates A and A an or-gate 0 a not-gate N and four gates G Gar, G and G, which serve as switches. These elements are interconnected in the manner shown in FIGURE 3. The gates G G21, G and G may be temporarily opened by the control circuit (not shown) by supplying control pulses C C C and C If desired, the said gates may be made manually controllable, although this will seldom be practical.

Since each function of the three variables x y, and 0 can be written in the form u E, ,-1-E c where a, and v-, are two functions of x and y the or-gate O, can deliver each function of x y, and c for which purpose the relevant functions It, and v can be written in the flipfiops U and V In the patent referred to above, it is disclosed that this is the ease for all the functions of x, and y, so that it is possible to form every function of x y and C1 1,1 at the output of the or-gate O This makes it pOsSi'ole to produce the carries in the peripheral equipment for the columns for all the digit positions sequentially and this as well for the addition as for the subtraction and independently of the fact whether or not an endaround carry is used. For this purpose it is necessary only previously to store the suitable signals in the flip-flops U and V and then to open all the gates G so that the carry can propagate over all the digit positions of the peripheral equipment. When using diode circuits for the or-, andand not-gates, the carry may be formed at all the digit positions of a computer member having 40 binary digit positions (corresponding to about 12 decimal digit positions) within one microsecond. The transfers carries formed in the peripheral equipment for the columns can be written in the storage matrix by opening the gates G The wires 2 are preferably connected to the storage elements of the columns of the storage matrix so that each carry is written in the column in which it has to be handled. The manner in which this may be effected is described in the patent repeatedly referred to above.

All the gates G being closed, the wire 31 1 i conveys a signal which is interpreted by the end-gate A as a signal of the value 0 and the wire 414,1 conveys a signal which is interpreted by the and-gate A as a signal of the value 1. All the and-gates A now supply output signals of the value- 0 whereas the and-gates A supply output signals of the same value as the signals stored in the corresponding flip-flops U The signals stored in the flip-flops U may be transferred to one or more rows, specially indicated in the storage matrix, by keeping all the gates G closed and opening all the gates G If the storage elements of the storage matrix are storage cores this may be efiected, as is well-known, in a very simple manner by using the coincidence principle.

It will now be described in detail in which manner the sum s of two numbers x and y may be formed with the equipment described. In this connection it is to be noted, however, that the difierence v of two numbers may be formed in an analogous manner.

To permit the use of the method of calculating illustrated in FIGURE 1, it is necessary first to produce signals identified with the carries. To this end, the signals p =x y and q i fi (i is the serial number of the relevant digit position) must be formed in accordance with the formulae given in FIGURE 2. The table in FIGURE 4 illustrates in which manner this may be effected.

For the process concerned use is made of five rows of the storage matrix, namely the rows 1, 2, 3, 4 and 5. In FIGURE 4 the number of each row is found in the column 1.

Not all the rows of the storage matrix are coupled to the peripheral equipment in the same manner and the way in which this coupling takes place is shown for each row separately by the symbol (a, ,8) specified in the readwrite column RW, where each of the two Greek characters a and {i may be 1 or O. The signals stored in a row for which a=1, upon reading such a row for the use of the peripheral equipment for the columns, are led to this peripheral equipment in uncomplemented form. This is intended to mean that, if a signal of the value 1 is stored at a given digit position of such a row, upon reading this row, a signal which is treated as a signal of the value 1 for the further handling is stored in the flip-flop U or V (dependent on whether the gates G or the gates G are emporarily opened) and that, if a signal of the value 0 is stored at this digit position, upon reading this row, a signal which is treated as a signal of the value 0 for the further handling is stored in the flip-flop U, or V The signals stored in a row for which ot=0, upon reading such a row for the use of the peripheral equipment for the columns, are transferred to this peripheral equipment in complemented form. This is intended to mean that, if a signal of the value 1 is stored at a given digit position of such a row, upon reading this row, a signal which is treated as a signal of the value 0, for the further handling is stored in the flip-flop U or V, (again dependent on whether the gates G or the gates G are transiently opened) and conversely.

The signals present in the wires 2 are stored in uncomplemented form in a row for which 3:1 and these signals are stored in complemented form in a row for which [3:0, which must naturally be interpreted in the abovementioned sense. If the storage elements are so-called storage cores the above result may be achieved by threading the reading wires in a suitable manner through the rows of the storage matrix and threading the writing wires 2 in a suitable manner through the columns of the storage matrix.

The circuit is controlled by pulses supplied by the control circuit and which may occur at two phases of the clock pulse cycles. A transport of signals from the storage matrix to the peripheral equipment for the columns can take place only during the phase 1 of a clock-pulse cycle (indicated by one accent in FIGURE 4) and a transport of signals in the opposite sense can take place only during the phase 2 of a clock-pulse cycle (indicated by a double accent in FIGURE 4). Signals are written or stored in the storage matrix preferably by using the so-called coincidence principle. This makes it possible for the signals present in the wires 2 to be stored in rows specially indicated of the matrix and this in uncomplemented form for the rows for which fi l and in complemented form for the rows for which 5:0. A row of the storage matrix can be read without the use of the coincidence principle.

The signals p =x y and q =5Q may be formed as follows: During the 0 pulse cycle and hence at the beginning of this operation, the first and second rows contain the signals x, and y, and all the other rows entering into account are empty, that is to say the storage cores of the row for which u=l are in the position 0 and the storage cores of the rows for which a=0 are in the position 1. During the first phase of the first pulse cycle, the row 1 is read and the signals stored in this row are thus transferred to the flip-flops U, in uncomplemented form. For this purpose it is necessary to open temporarily the gates G during this phase (presence of the pulse C During the second phase of the first pulse cycle, the signals stored in the flip-flops U, are transferred to the rows 1, 3 and 4 of the storage matrix which thus contain the signals x x and 5 It is necessary therefore that, during this phase, all the gates G are temporarily opened but all the gates G remain closed (presence of the pulse C but absence of the pulse C During the first phase of the second pulse cycle, the row 2 is read and the signals stored in this row are transferred to the flip-flops U, (gates G open). During the second phase of the second pulse cycle, the signals stored in the flip-flops U, are transferred to the rows 2, 3 and 4 of the storage matrix (gates G open but gates G closed). The signals y are thus rewritten in the row 2. Since the row 3 already contained the signals x this row contains the signals x,vy,=' after the end of the second clock pulse cycle. Since the row 4 already contained the signals 5,, this row contains the signals 5,v5j,=5, after the end of the second clock pulse cycle. The signals 1 stored in the row 4 are transferred to the flip-flops U; in uncomplemented form during the first phase of the third cycle of clock pulses and the signals 5, stored in the flip-flops U, are supplied back to the row 4 in complemented form during the second phase of the third cycle of clock pulses, so that this row contains the signals p, after the end of the third cycle of clock pulses. The signals 5 stored in the row 3 are transferred to the flip-flops U, in uncomplemented form during the first phase of the fourth clock pulse cycle and the signals stored in the flip-flops U, are transferred to the row 5 in complemented form during the second phase of the fourth clock pulse cycle, so that this row contains the signals q after the end of the fourth clock pulse cycle. The process above described can be followed step by step in the lefthand part of FIGURE 4. The right-hand part of this figure is an abbreviated notation-for the same.

FIGURE 5 illustrates, with the use of this abbreviated notation, in which manner the sum s of two numbers x and y may be formed in eleven cycles of clock pulses. The first four clock pulse cycles are used to form the signals p and q, in the manner just described. During the clock pulse cycle 5, the signal q, is transferred from the row 5 to the rows 3 and 6. During the clock pulse cycle 6, the signal p, is transferred from the row 4 to the row 3 which thus now contains the signal p Vq =7 Of the clockpulse cycle 7 only the reading phase is used to transfer the signal q, from the row 6 to the flip-flop V So the flip-flops U and V now contain the signals p and q The writing phase of the clock-pulse cycle 7 and the reading phase of the clock-pulse cycle 8 are used to enable the carry to propagate over all the digit positions. For this purpose the final part of the reading phase of clockpulse cycle 7 may possibly be suificient which would save one clock-pulse cycle. The writing-phase of the clockpulse cycle 8 is used to write the carry 014,1 formed in the meantime, in uncomplemented form in the row 7 and in complemented form in the row 8. During the clockpulse cycle 9, the signal F, of row 3 is transferred in uncomplemented form to the row 7 and in complemented form to the row 8, which rows thus now contain the signals F veand r VE, During the clock-pulse cycle 10, the signal EVE is transferred in complemented form from the row 7 to the row 3, which thus contains the signal F Vc =r E During the clock-pulse phase 11, the signal W5 is transferred in complemented form from the row 8 to row 3, which thus contains the signal "1 1-1,1 1 i 1,1= 1 1-1,1 i1-1,1= 1 The addition is thus completed.

Summarizing the foregoing example, the following sequence describes the summation operation:

(1) Read: x (Row 1) to U (Gate G opened).

Write: U signal (x,) to Rows 1, 2, and Z (gates 3 open, 4, closed). (The not sign over a row number will be used to signify that a transfer has has been made in its complement.) Here, this means that x has been written in Rows 1 and 3, While 5, in Row 4. In FIG. 4, the RW column contains this complementing information. (2) Read: y, (Row 2) to U (Gate G open).

Write: U, (y) to Rows 2, 3, 4. As a result y is written in Row 2; x vy is formed in Row 3 (E and since 5 was in Row Z, 5 is formed (1). (Note: p and q designations are arbitrarily assigned: see FIG. 2). (3) Read: 1 (Row 4) to U Write: U, to Row 1. Row 4 now contains 11 or p; (4) Read: 5, (Row 3) to U Write: U to Row 5. Row 5 now contains 11 or q,.

Note that the partial or intermediate values q and p, are now formed and stored in the memory. For simplicity the read Write dichotomy format Will be dispensed with where obvious in the remaining discussion of the operation of the remaining clock cycles.

(5) q, transferred from Row 5 to Rows 3 and 6. (6) p transferred from Row 4 to Row 3.

Row 3 now contains p vq or 7 (7) Read: q, from Row 6 to v,. v, now contains q whereas U still has p therein. At this point, the logic circuit is now primed to generate the carry signal for the next successive logic stage, whereas the carry signal from the last successive logic stage is available for use. These operations are assumed to absorb the write cycle time of pulse 7 and read time of pulse 8.

(8) Write: carry c into Row 7 and 5 to Row 8.

(9) F transferred from Row 3 to Row 7 and Row S,

Row 7 now contains F Vc Row 8 now contains T1VE1 1 OI r VE (l0) F Vc transferred from Row 7 to Row 3, Row 3 now contains (F Vc or r 5 (11) r VE transferred from Row 8 to Row 3, Row 3 It has previously been stated hereinbefore that the signals c and 51,1 formed sequentially in the peripheral equipment for the columns need not necessarily have the significance of the carry in an addition or subtraction. In fact, there are logical processes which need not have arithmetic significance but may be decomposed, as the addition and the subtraction, into a part which may be carried out simultaneously and a part which may be carried out sequentially, or which even do not contain a part which may be carried out simultaneously.

An example of such a process is the determination of the parity of the number of digits 1 of a number. When the signals x are stored in the flip-flops U, as well as in the flip-flops V it is found that at each digit position for which x,-=1, the following formula is fulfilled:

and that at the digit positions for which x =0, there is fulfilled the formula:

These results, which may be readily deduced from the circuit shown in FIGURE 3, are summarized in the table of FIGURE 6. This may be expressed by saying that the signal c is complemented when passing a digit position for which x =1, but is not complemented when passing a digit position for which x =0. So the fact whether the signal formed at the latter digit position is complemented or not with respect to the signal introduced at the first digit position is an indication of whether, the relevant number comprises an odd or an even number of digits 1.

In the described example of the addition only the logical operations not and or are established in the storage matrix and the logical operation and is reduced to these two. The whole may, of course be so designed that other primitive logical operations can be performed directly in the storage matrix in the manner described in the patent repeatedly referred to. This makes the wiring thereof a little more complicated but may give the machine a higher speed because fewer clock pulse cycles are then required for an addition or a subtraction.

It is noted that the invention is also applicable to computers calculating in a system other than the binary systern. In a computer calculating in the decimal system, in

which the so-called excess-three code is used, this may take place almost Without modifications since this code is a disguised binary code. When using other codes, however several unessential and evident modifications are necessary.

It is also pointed out that, under certain conditions, it is possible to simplify the circuit shown in FIGURE 3 by omitting the flip-flop V, and connecting the upper inlet of the and-gate A to the left-hand outlet of the flip-flop U In this case, however, only the signals of the form u c ii c can be formed, thus reducing the possibilities of the circuit.

It is further noted that each of the gates G and 6 can be doubled so that a signal received from the storage matrix can be written in the flip-flop U, or V, in uncomplemented or complemented form. With the present state of the art, however, it is more advantageous to use for this purpose a few additional rows of the storage matrix as above described.

What is claimed is:

1. An arrangement for forming digital summations from sum and carry component signals and comprising a multidigit storage matrix having a plurality of rows of storage elements for the retention of a plurality of digits arranged in a sequentially ordered multidigit array, and a plurality of information transfer control means, each associated with one digit order of said multi-order sequence and connected to said matrix, each said control means comprising a temporary bistable storage means, a multi-input logic circuit for forming an intermediate signal representative of said sum and carry component signals, first switching means connecting said matrix to the input of said bistable storage means for forming said sum component signal, second switching means connecting the output of said logic circuit to said matrix, means connecting one input of said logic circuit to the output of said bistable storage means for receiving said sum component signal, means connecting another input of said logic circuit to the output of the preceding logic circuit associated with the last digit order position in descending order of significance for receiving said carry component signal, third switching means connecting the output of said logic circuit to an input of the succeeding logic circuit associated with the next digit order position in ascending order of significance for supplying thereto the next digit order carry component signal, means successively applying control signals to said first, second and third switching means respectively to initiate and maintain information transfer to and from said matrix through each said control mean-s in a predetermined sequence to form said sum component signal for one order digit and said carry component signal for the next order digit in ascending order of significance.

2. A computer for performing an arithmetic operation between first and second binary coded digits and comprising a multidigit storage matrix having a plurality of rows of storage elements for retention of a plurality of digits arranged in a sequentially ordered multidigit array, and a plurality of information transfer control means, each associated with one digit order of said multiorder sequence and connected to said matrix, each said control means comprising first and second bistable storage means and a multi-input logic circuit, said first bistable storage means storing a signal a, and said second bistable storage means storing a signal v wherein i represents the relative order position of respective ones of said first and second digits, first switching means connecting an output of each of said first and second bistable storage means to said matrix, second switching means connecting the output of said logic circuit to said matrix, means connecting respective inputs of said logic circuit to respective outputs of ceding logic circuit associated with the preceding digit order position in descending order of significance, third switching means connecting the output of said multi-input logic circuit to an input of the succeeding logic circuit associated with the next digit order position in ascending order of significance, means applying control pulses to said first, second and third switching means to initiate and maintain information transfer to and from select rows of said matrix through each said control means over a predetermined period and in a predetermined sequence to form a first component signal for one order digit 1', said logic circuit including sum and product gates arranged to be responsive to the said applied inputs to form a second arithmetic component signal for the digit order 1' +1 of the form wherein;

u, is the output of said first bistable storage means,

0 is the complemented output of said preceding digit logic circuit in descending order of significance,

v, is the complemented output of said second bistable storage means, and

0 is the output of said preceding digit logic circuit in descending order of significance, means applying the output of said next most significant digit logic circuit in descending order to said matrix during said predetermined period to complete the said arithmetic addition in the signal form, and means connecting the output of said multi-stage logic circuit to the input of the logic circuit in the next higher digit positron stage in ascending order of significance, and means applying the second arithmetic component signal associated with the logic circuit of the preceding digit i-l in descending order of significance and the said first arithmetic component signal associated with the order i to said matrix to complete said arithmetic operation.

3. The combination of claim 2 wherein said data signal represents the resultant of an arithmetic summing operation and said first and second component signals represent sum and carry signals respectively.

4. A computer for performing an arithmetic addition between first and second multidigit binary coded numbers x and y and comprising a multidigit capacity storage matrix having a plurality of rows of storage elements for the retention of a plurality of digits arranged in a sequentially ordered multi-digit array and information transfer control means connected to said matrix, said control means comprising first and second bistable flip-flops and a present stage multi-input logic gate including an OR gate and a pair of AND gates having first and second respective outputs connected to the inputs of said OR gate, said AND gates being connected to the output and comple mentary output respectively of said first and second fii-pfiops, switching means connecting the inputs of said flipfiops to said matrix, means for applying control signals to said switching means to initiate and maintain information transfer to and from said matrix through said first and second bistable means over a predetermined period and in a predetermined sequence until the signals r; and E are formed in said matrix wherein r =x y vx y and am s/5,5,, and the signals p and q, are formed in said first and second flip-flops respectively, wherein p =x y and q =55 means respectively connecting further inputs of said AND gates to the logic circuit output, and the complement thereof, associated with the preceding bit position in descending order of significance, said logic circuit responsive to all of said inputs to form the signal 5 is the complemented output of said preceding digit logic circiut in descending order 5 is the complemented output of said second flip-flop and represents x vy and C is the output of the said preceding digit logic circuit in descending order, means applying the output of said next most significant digit logic circuit in descending order to said matrix during said predetermined period to compute the said arithmetic addition in the signal form wherein s is the final arithmetic summation, and means connecting the output c of the present stage logic circuit to the input of the logic circuit in the succeeding digit position stage in ascending order of significance.

References Cited UNITED STATES PATENTS 3,166,669 1/1965 Cochrane 23 5175 3,202,806 8/1965 Menne 235175 3,234,371 2/1966 Osofsky 235-175 MALCOLM A. MORRISON, Primary Examiner. I. J. FAIBISCH, V. SIBER, Assistant Examiners.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,369,110 February 13, 1968 Herman Jacob Heijn It is certified that error appears in the above identified patent and that said Letters Patent are hereby corrected as shown below:

Column 8, line 5, "output" should read input line 10, "ceding" should read each of said bistable means and to the output of the preceding line 30, "c should I i-l,i read C line 32, "v should read i-l ,i 1 i line 73, "r =x y Vx y should read r =X V y Column 9, line 15, "circiut" should read circuit Signed and sealed this 6th day of January 1970.

(SEAL) Attest:

EDWARD M.FLETCHER,JR. WILLIAM E. SCHUYLER, JR.

Attesting Officer Commissioner of Patents 

1. AN ARRANGEMENT FOR FORMING DIGITAL SUMMATIONS FROM SUM AND CARRY COMPONENT SIGNALS AND COMPRISING A MULTIDIGIT STORAGE MATRIX HAVING A PLURALITY OF ROWS OF STORAGE ELEMENTS OF THE RETENTION OF A PLURALITY OF DIGITS ARRANGED IN A SEQUENTIALLY ORDERED MULTIDIGIT ARRAY, AND A PLURALITY OF INFORMATION TRANSFER CONTROL MEANS, EACH ASSOCIATED WITH ONE DIGIT ORDER OF SAID MULTI-ORDER SEQUENCE AND CONNECTED TO SAID MATRIX, EACH SAID CONTROL MEANS COMPRISING A TEMPORARY BISTABLE STORAGE MEANS, A MULTI-INPUT LOGIC CIRCUIT FOR FORMING AN INTERMEDIATE SIGNAL REPRESENTATIVE OF SAID SUM AND CARRY COMPONENT SIGNALS, FIRST SWITCHING MEANS CONNECTING SAID MATRIX TO THE INPUT OF SAID BISTABLE STORAGE MEANS FOR FORMING SAID SUM COMPONENT SIGNAL, SECOND SWITCHING MEANS CONNECTING THE OUTPUT OF SAID LOGIC CIRCUIT TO SAID MATRIX, MEANS CONNECTING ONE INPUT OF SAID LOGIC CIRCUIT OF THE OUTPUT OF SAID BISTABLE STORAGE MEANS FOR RECEIVING SAID SUM COMPONENT SIGNAL, MEANS CONNECTING ANOTHER INPUT OF SAID LOGIC CIRCUIT TO THE OUTPUT OF THE PRECEDING LOGIC CIRCUIT ASSOCIATED WITH THE LAST DIGIT ORDER POSITION IN DESCENDING ORDER OF SIGNIFICANCE FOR RECEIVING SAID CARRY COMPONENT SIGNAL, THIRD SWITCHING MEANS CONNECTING THE OUTPUT OF SAID LOGIC CIRCUIT TO AN INPUT OF THE SUCCEEDING LOGIC CIRCUIT ASSOCIATED WITH THE NEXT DIGIT ORDER POSITION IN ASCENDING ORDER OF SIGNIFICANCE FOR SUPPLYING THERETO THE NEXT DIGIT ORDER CARRY COMPONENT SIGNAL, MEANS SUCCESSIVELY APPLYING CONTROL SIGNALS TO SAID FIRST, SECOND AND THIRD SWITCHING MEANS RESPECTIVELY TO INITIATE AND MAINTAIN INFORMATION TRANSFER TO AND FROM SAID MATRIX THROUGH EACH SAID CONTROL MEANS IN A PREDETERMINED SEQUENCE TO FORM SAID SUM COMPONENT SIGNAL FOR ONE ORDER DIGIT AND SAID CARRY COMPONENT SIGNAL FOR THE NEXT ORDER DIGIT IN ASCENDING ORDER OF SIGNIFICANCE. 